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CS4334/5/6/7/8/9
8-Pin, 24-Bit, 96 kHz Stereo D/A Converter
Features
l Complete Stereo DAC System: Interpolation,
Description
The CS4334 family members are complete, stereo digital-to-analog output systems including interpolation, 1-bit D/A conversion and output analog filtering in an 8-pin package. The CS4334/5/6/7/8/9 support all major audio data interface formats, and the individual devices differ only in the supported interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power supply, and requires minimal support circuitry. These features are ideal for set-top boxes, DVD players, SVCD players, and A/V receivers. ORDERING INFORMATION See page 23
D/A, Output Analog Filtering l 24-Bit Conversion l 96 dB Dynamic Range l -88 dB THD+N l Low Clock Jitter Sensitivity l Single +5 V Power Supply l Filtered Line Level Outputs l On-Chip Digital De-emphasis l Popgaurd(R) Technology l Functionally Compatible with CS4330/31/33
I
DEM/SCLK 2 LRCK SDATA 3 1 Serial Input Interface De-emphasis
AGND 6
VA 7
Voltage Reference
Interpolator
Modulator
DAC
Analog Low-Pass Filter
8
AOUTL
Interpolator
Modulator 4 MCLK
DAC
Analog Low-Pass Filter
5
AOUTR
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1999 (All Rights Reserved)
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CS4334/5/6/7/8/9
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ...................................................... 4 ANALOG CHARACTERISTICS................................................................... 4 POWER AND THERMAL CHARACTERISTICS ......................................... 6 DIGITAL CHARACTERISTICS.................................................................... 7 ABSOLUTE MAXIMUM RATINGS .............................................................. 7 RECOMMENDED OPERATING CONDITIONS .......................................... 7 SWITCHING CHARACTERISTICS ............................................................. 8 2. TYPICAL CONNECTION DIAGRAM ........................................................... 10 3. GENERAL DESCRIPTION .......................................................................... 11 3.1 Digital Interpolation Filter ................................................................... 11 3.2 Delta-Sigma Modulator ...................................................................... 11 3.3 Switched-Capacitor DAC ................................................................... 11 3.4 Analog Low-Pass Filter ...................................................................... 11 4. SYSTEM DESIGN ........................................................................................ 12 4.1 Master Clock ...................................................................................... 12 4.2 Serial Clock ........................................................................................ 12 4.2.1 External Serial Clock Mode ...................................................... 12 4.2.2 Internal Serial Clock Mode ....................................................... 12 4.3 De-Emphasis ..................................................................................... 12 4.4 Initialization and Power-Down ........................................................... 12 4.5 Output Transient Control ................................................................... 13 4.6 Grounding and Power Supply Decoupling ......................................... 13 4.7 Analog Output and Filtering ............................................................... 13 4.8 Overall Base-Rate Frequency Response .......................................... 17 4.9 Overall High-Rate Frequency Response ........................................... 18 4.10 Base Rate Mode Performance Plots ............................................... 19 4.11 High Rate Mode Performance Plots ................................................ 20 5. PIN DESCRIPTIONS ................................................................................... 21 6. PARAMETER DEFINITIONS ....................................................................... 22 7. REFERENCES ............................................................................................. 22 8. ORDERING INFORMATION: ...................................................................... 23 9. FUNCTIONAL COMPATIBILITY ................................................................. 23 10. PACKAGE DIMENSIONS .......................................................................... 24
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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LIST OF FIGURES
Figure 1.Output Test Load .................................................................................... 6 Figure 2.Maximum Loading................................................................................... 6 Figure 3.Power vs. Sample Rate .......................................................................... 6 Figure 4.External Serial Mode Input Timing.......................................................... 9 Figure 5.Internal Serial Mode Input Timing ........................................................... 9 Figure 6. Internal Serial Clock Generation ............................................................ 9 Figure 7.Recommended Connection Diagram.................................................... 10 Figure 8.System Block Diagram.......................................................................... 11 Figure 9.De-Emphasis Curve (Fs = 44.1kHz) ..................................................... 13 Figure 10.CS4334 Data Format (I2S).................................................................. 14 Figure 11.CS4335 Data Format .......................................................................... 14 Figure 12.CS4336 Data Format .......................................................................... 14 Figure 13.CS4337 Data Format .......................................................................... 15 Figure 14.CS4338 Data Format .......................................................................... 15 Figure 15.CS4339 Data Format .......................................................................... 15 Figure 16.CS4334/5/6/7/8/9 Initialization and Power-Down Sequence .............. 16 Figure 17.Stopband Rejection............................................................................. 17 Figure 18.Transition Band................................................................................... 17 Figure 19.Transition Band................................................................................... 17 Figure 20.Passband Ripple................................................................................. 17 Figure 21.Stopband Rejection............................................................................. 18 Figure 22.Transition Band................................................................................... 18 Figure 23.Transition Band................................................................................... 18 Figure 24.Passband Ripple................................................................................. 18 Figure 25.0 dBFS FFT (BRM) ............................................................................. 19 Figure 26. -60 dBFS FFT (BRM)......................................................................... 19 Figure 27.Idle Channel Noise FFT (BRM)........................................................... 19 Figure 28.Twin Tone IMD FFT (BRM)................................................................. 19 Figure 29.THD+N vs. Amplitude (BRM) .............................................................. 19 Figure 30.THD+N vs. Frequency (BRM) ............................................................. 19 Figure 31.0 dBFS FFT (HRM)............................................................................. 20 Figure 32. -60 dBFS FFT (HRM)......................................................................... 20 Figure 33.Idle Channel Noise FFT (HRM) .......................................................... 20 Figure 34.Twin Tone IMD FFT (HRM) ................................................................ 20 Figure 35.THD+N vs. Amplitude (HRM).............................................................. 20 Figure 36. THD+N vs. Frequency (HRM)............................................................ 20
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1. CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 C; Logic "1" = VA = 5 V; Logic "0" = AGND;
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load RL = 10 k, CL = 10 pF (see Figure 1)) Base-rate Mode Parameter Symbol Min -10 88 91 86 89 -40 85 88 83 86 Typ 93 96 91 94 -88 -73 -33 -86 -71 -31 94 93 96 91 94 -88 -73 -33 -86 -71 -31 94 Max 70 -83 -68 -28 -81 -66 -26 85 -82 -65 -25 -70 -63 -23 High-Rate Mode Min -10 91 89 -40 88 86 Typ 90 96 88 94 -88 -70 -30 -86 -68 -28 95 90 96 88 94 -88 -70 -30 -86 -68 -28 95 Max 70 -83 -65 -25 -81 -63 -23 85 -82 -62 -22 -80 -60 -20 Unit C dB dB dB dB dB dB dB dB dB dB dB C dB dB dB dB dB dB dB dB dB dB dB
Dynamic Performance for CS4334/5/6/7/8/9-KS Specified Temperature Range TA Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted Total Harmonic Distortion + Noise (Note 1) THD+N 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Dynamic Performance for CS4334/5/6/7/8/9-BS Specified Temperature Range TA Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted Total Harmonic Distortion + Noise (Note 1) THD+N 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz)
Notes: 1. One-half LSB of triangular PDF dither added to data.
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ANALOG CHARACTERISTICS (Continued)
Base-rate Mode High-Rate Mode Parameter Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response (Note 2) Passband (Note 3) to -0.05 dB corner 0 .4780 Fs to -0.1 dB corner 0 .4650 Fs to -3 dB corner 0 .4996 0 .4982 Fs Frequency Response 10 Hz to 20 kHz -.01 +.08 -.05 +.2 dB Passband Ripple .08 .2 dB StopBand .5465 .5770 Fs StopBand Attenuation (Note 4) 50 55 dB Group Delay tgd 9/Fs 4/Fs s Passband Group Delay Deviation 0 - 40 kHz 0.36/Fs 1.39/Fs s 0 - 20 kHz 0.23/Fs s +1.5/+0 dB De-emphasis Error Fs = 32 kHz +.05/-.25 (Note 5) dB Fs = 44.1 kHz -.2/-.4 dB Fs = 48 kHz Parameters dc Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Analog Output Full Scale Output Voltage Quiescent Voltage Max AC-Load Resistance Max Load Capacitance Symbol Min 3.25 Typ 0.1 5 100 3.5 2.2 3 100 Max 0.4 3.75 Units dB % ppm/C Vpp VDC k pF
(Note 6) (Note 6)
VQ RL CL
Notes: 2. Filter response is not tested but is guaranteed by design. 3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 17-24) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is not available in High-Rate Mode. 6. Refer to Figure 2.
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POWER AND THERMAL CHARACTERISTICS
Parameters Power Supplies Power Supply Current Power Dissipation Symbol normal operation power-down state (Note 7) normal operation power-down (1 kHz) IA IA Min Typ 15 40 75 0.2 110 79 Max 19 104 Units mA A mW mW C/Watt dB
Package Thermal Resistance Power Supply Rejection Ratio
JA PSRR
Notes: 7. Refer to Figure 3. Max Power Dissipation is measured at VA=5.5V.
10 F AOUTx R C V out L L
AGND
Figure 1. Output Test Load
125 Capacitive Load -- C L (pF) 100
75 70 Power (mW) 65
HR
M BR
75 50 25 Safe Operating Region
M
60 55 50 30 40 50 60 70 80 Sample Rate (kHz) 90 100
2.5 3
5
10
15
20
Resistive Load -- RL (k)
Figure 2. Maximum Loading
Figure 3. Power vs. Sample Rate
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DIGITAL CHARACTERISTICS (TA = 25C; VA = 4.75V - 5.5V)
Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Notes: 8. Iin for CS433X LRCK is 20A max. Symbol VIH VIL Iin Min 2.0 Typ 8 Max 0.8 10 Units V V A pF
(Note 8)
ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.)
Parameters DC Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA Iin VIND TA Tstg Min -0.3 -0.3 -55 -65 Max 6.0 10 VA+0.4 125 150 Units V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
Parameters DC Power Supply Symbol VA Min 4.75 Typ 5.0 Max 5.5 Units V
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SWITCHING CHARACTERISTICS (TA = -40 to 85C; VA = 4.75V - 5.5V; Inputs: Logic 0 = 0V,
Logic 1 = VA, CL = 20pF) Parameters Input Sample Rate MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width Low MCLK Pulse Width Low MCLK/LRCK = 512 MCLK/LRCK = 512 MCLK / LRCK = 384 or 192 MCLK / LRCK = 256 or 128 Symbol Fs Min 2 10 10 21 21 31 31 40 tsclkl tsclkh tsclkw tsclkw tslrd tslrs tsdlrs tsdh (Note 9) (Note 10) tsclkw tsclkr tsdlrs tsdh tsdh 20 20
1 --------------------( 128 )Fs 1 -----------------( 64 )Fs
Typ 50 50 tsclkw ----------------2
Max 100 1000 1000 1000 1000 1000 1000 60 -
Units kHz ns ns ns ns ns ns % ns ns ns ns ns ns ns ns % ns s ns ns ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192 MCLK Pulse Width High MCLK / LRCK = 256 or 128
External SCLK Mode LRCK Duty Cycle (External SCLK only) SCLK Pulse Width Low SCLK Pulse Width High SCLK Period MCLK / LRCK = 512, 256 or 384
SCLK Period MCLK / LRCK = 128 or 192
SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time
20 20 20 20 1 ---------------SCLK
Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) SCLK Period
SCLK rising to LRCK edge SDATA valid to SCLK rising setup time
1 --------------------- + 10 ( 512 )Fs 1 --------------------- + 15 ( 512 )Fs
-
SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192
1 --------------------- + 15 ( 384 )Fs
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% +/- 1/2 MCLK Period. 10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK ratio. (See figures 10-15)
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LRCK t slrd t slrs t sclkl t sclkh
SCLK t sdlrs
SDATA
t sdh
Figure 4. External Serial Mode Input Timing
LRCK
t sclkr
SDATA t sclkw t sdlrs *INTERNAL SCLK t sdh
Figure 5. Internal Serial Mode Input Timing * The SCLK pulses shown are internal to the CS4334/5/6/7/8/9.
LRCK
MCLK 1
*INTERNAL SCLK
N 2
N
SDATA
Figure 6. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4334/5/6/7/8/9. N equals MCLK divided by SCLK
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2. TYPICAL CONNECTION DIAGRAM
+ 7 VA 1 Audio Data Processor 2 3 0.1 F 1 F
+5V
SDATA 8 DEM/SCLK LRCK AOUTL 267 k
3.3 F + 10 k
560 Left Audio Output C RL
CS4334 CS4335 CS4336 CS4337 CS4338 CS4339 3.3 F AOUTR External Clock 4 MCLK 5 + 267 k 10 k C 560 Right Audio Output RL
AGND 6
C=
R L + 560 4Fs(R L560)
Figure 7. Recommended Connection Diagram
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3. GENERAL DESCRIPTION
The CS4334 family of devices offers a complete stereo digital-to-analog system including digital interpolation, fourth-order delta-sigma digital-to-analog conversion, digital de-emphasis and analog filtering, as shown in Figure 8. This architecture provides a high tolerance to clock jitter. The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of resistive laser trimmed digital-to-analog converter architectures by using an inherently linear 1-bit digital-to-analog converter. The advantages of a 1bit digital-to-analog converter include: ideal differential linearity, no distortion mechanisms due to resistor matching errors and no linearity drift over time and temperature due to variations in resistor values. The CS4334 family of devices supports two modes of operation. The devices operate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192. High Rate Mode allows input sample rates up to 100 kHz. filter eliminates images of the baseband audio signal which exist at multiples of the input sample rate. The resulting frequency spectrum has images of the input signal at multiples of 4 Fs. These images are easily removed by the on-chip analog lowpass filter and a simple external analog filter (see Figure 7).
3.2 Delta-Sigma Modulator
The interpolation filter is followed by a fourth order delta-sigma modulator which converts the interpolation filter output into 1-bit data at a rate of 128 Fs in BRM (or 64 Fs in HRM).
3.3 Switched-Capacitor DAC
The delta-sigma modulator is followed by a digitalto-analog converter which translates the 1-bit data into a series of charge packets. The magnitude of the charge in each packet is determined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit data. This technique greatly reduces the sensitivity to clock jitter and provides low-pass filtering of the output.
3.1 Digital Interpolation Filter
The digital interpolation filter increases the sample rate, Fs, by a factor of 4 and is followed by a 32x digital sample-and-hold (16x in HRM). This
3.4 Analog Low-Pass Filter
The final signal stage consists of a continuous-time low-pass filter which serves to smooth the output and attenuate out-of-band noise.
Digital Input
Interpolator
Delta-Sigma Modulator
DAC
Analog Low-Pass Filter
Analog Output
Figure 8. System Block Diagram
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4. SYSTEM DESIGN
The CS4334 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in BRM and 96, 88.2 and 64 kHz in HRM. Audio data is input via the serial data input pin (SDATA). The Left/Right Clock (LRCK) defines the channel and delineation of data, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4334/5/6/7/8/9 differ in serial data formats as shown in Figures 10-15.
4.2.1 External Serial Clock Mode
The CS4334 family will enter the External Serial Clock Mode when 16 low to high transitions are detected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock Mode and de-emphasis filter cannot be accessed. The CS4334 family will switch to Internal Serial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames of LRCK. Refer to Figure 16.
4.1 Master Clock
MCLK must be either 256x, 384x or 512x the desired input sample rate in BRM and either 128x or 192x the desired input sample rate in HRM. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal dividers are set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous.
LRCK (kHz) 32 44.1 48 64 88.2 96 MCLK (MHz) HRM BRM 128x 192x 256x 384x 512x 4.0960 6.1440 8.1920 12.2880 16.3840 5.6448 8.4672 11.2896 16.9344 22.5792 6.1440 9.2160 12.2880 18.4320 24.5760 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 Table 1. Common Clock Frequencies
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data format. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital de-emphasis function. Refer to Figures 10 - 16 for details. While the Internal Serial Clock Mode is provided to allow access to the de-emphasis filter, the Internal Serial Clock Mode also eliminates possible clock interference from an external SCLK.
4.3 De-Emphasis
The CS4334 family includes on-chip digital de-emphasis. Figure 9 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges of LRCK. This function is available only in the internal serial clock mode.
4.2 Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4334 family supports both external and internal serial clock generation modes. Refer to Figures 10-15 for data formats.
4.4 Initialization and Power-Down
The Initialization and Power-Down sequence flow chart is shown in Figure 16. The CS4334 family enters the Power-Down State upon initial power-up.
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Gain dB T1=50 s 0dB
capacitor to charge to VQ, effectively blocking the quiescent DC voltage. To prevent transients at power-down, the device must first enter its power-down state. This is accomplished by removing MCLK or LRCK. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. A soft-start current sink is substituted in place of AOUTL and AOUTR which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on. To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the powerdown state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 F capacitor, the time that the device must remain in the power-down state will be approximately 0.4 seconds.
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
The interpolation filters and delta-sigma modulators are reset, and the internal voltage reference, one-bit digital-to-analog converters and switchedcapacitor low-pass filters are powered down. The device will remain in the Power-Down mode until MCLK and LRCK are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and switchedcapacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ.
4.5 Output Transient Control
The CS4334 family uses Popgaurd(R) technology to minimize the effects of output transients during power-up and power-down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation. When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. After a short delay of approximately 1000 sample periods, each output begins to ramp towards its quiescent voltage, VQ. Approximately 10,000 sample cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking
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4.6 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4334 family requires careful attention to power supply and grounding arrangements to optimize performance. Figure 7 shows the recommended power arrangement with VA connected to a clean +5V supply. For best performance, decoupling capacitors should be located as close to the device package as possible with the smallest capacitor closest.
4.7 Analog Output and Filtering
The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 17 - 24.
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LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode I2 S, 16-Bit data and INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 I2S, Up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192 I2
External SCLK Mode S, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 10. CS4334 Data Format (I2S)
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode Left Justified, up to 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Left Justified, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 11. CS4335 Data Format
LRCK
Left Channel
Right Channel
SCLK
SDATA
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
32 clocks
Internal SCLK Mode Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 12. CS4336 Data Format
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LRCK
Left Channel
Right Channel
SCLK
SDATA
10
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode Right Justified, 20-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Right Justified, 20-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 40 Cycles per LRCK Period
Figure 13. CS4337 Data Format
LRCK
Left Channel
Right Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 14. CS4338 Data Format
LRCK
Left Channel
Right Channel
SCLK
SDATA
10
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode Right Justified, 18-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Right Justified, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 36 Cycles per LRCK Period
Figure 15. CS4339 Data Format
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Figure 16. CS4334/5/6/7/8/9 Initialization and Power-Down Sequence
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4.8 Overall Base-Rate Frequency Response
Figure 17. Stopband Rejection
Figure 18. Transition Band
0.1
0.08
0.06
Amplitude dB
0.04
0.02
0
0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (normalized to Fs) 0.4 0.45
Figure 19. Transition Band
Figure 20. Passband Ripple
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4.9 Overall High-Rate Frequency Response
Figure 21. Stopband Rejection
Figure 22. Transition Band
0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (normalized to Fs) 0.4 0.45
Figure 23. Transition Band
Amplitude dB
Figure 24. Passband Ripple
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4.10 Base Rate Mode Performance Plots
+0 +0 +0 -10 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 -50 -50 -50 -60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
+0 +0 +0 -10 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 -50 -50 -50 -60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
dBr A dBr A
d B r A
-100 -100 -100 -110 -110 -110 -120 -120 -120 -130 -130 -130 -140 -140 -140
2k 2k 2k
4k 4k 4k
6k 6k 6k
8k 8k 8k
10k 10k 10k Hz Hz Hz
12k 12k 12k
14k 14k 14k
16k 16k 16k
18k 18k 18k
20k 20k 20k
dBr A dBr A
d B r A
-100 -100 -100 -110 -110 -110 -120 -120 -120 -130 -130 -130 -140 -140 -140
20k
2k 2k 2k
4k 4k 4k
6k 6k 6k
8k 8k 8k
10k 10k 10k Hz Hz Hz
12k 12k 12k
14k 14k 14k
16k 16k 16k
18k 18k 18k
20k 20k 20k
(16k FFT of a 1 kHz input signal)
(16k FFT of a 1 kHz input signal)
Figure 25. 0 dBFS FFT (BRM)
+0 +0 +0 -10 -10 -10 -20 -20 -20 -30 -30 -30
-40 -40 -40 -50 -50 -50 -60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
Figure 26. -60 dBFS FFT (BRM)
+0 +0 +0 -10 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 -50 -50 -50
dBr A dBr A
dBr A dBr A
d B r A
d B r A
-60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
-100 -100 -100 -110 -110 -110 -120 -120 -120 -130 -130 -130
-100 -100 -100 -110 -110 -110 -120 -120 -120 -130 -130 -130
2k 2k 2k 4k 4k 4k 6k 6k 6k 8k 8k 8k 10k 10k 10k Hz Hz Hz 12k 12k 12k 14k 14k 14k 16k 16k 16k 18k 18k 18k 20k 20k 20k
-140 -140
-140
-140 -140 -140
2k 2k 2k
4k 4k 4k
6k 6k 6k
8k 8k 8k
10k 10k 10k Hz Hz Hz
12k 12k 12k
14k 14k 14k
1 6k 16k 16k
18k 18k
18k
20k 20k
20k
(16k FFT with no input signal)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 27. Idle Channel Noise FFT (BRM)
Figure 28. Twin Tone IMD FFT (BRM)
-60 -60
+0 +0 +0 -10 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40
-70 -70
dBr A
dBr AA dBr
d B r A
d B r A
-80 -80
-50 -50 -50 -60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
-90 -90
-100 -100
-100 -100 -100
-110 -110 -60 -60
-50 -50
-40 -40
-30 -30
dBFS dBFS
-20 -20
-10 -10
+0 +0
-110 -110 -11020 20 20
50 50 50
100 100
100
200 200 200
500 500 500 Hz Hz Hz
1k 1k 1k
2k 2k 2k
5k 5k 5k
10k 10k 10k
20k 20k 20k
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 29. THD+N vs. Amplitude (BRM)
Figure 30. THD+N vs. Frequency (BRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain System Two Cascade.
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4.11 High Rate Mode Performance Plots
+ +0 +00 -10 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 -50 -50 -50 -60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
+0 +0 +0 -10 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 -50 -50 -50 -60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
dBr A dBr A
d B r A
-100 -100 -100 -110 -110 -110 -120 -120 -120 -130 -130 -130 -140 -140 -140
dBr A A dBr
d B r A
-100 -100 -100 -110 -110 -110 -120 -120 -120 -130 -130 -130 -140 -140 -140
2k 2k 2k
4k 4k 4k
6k 6k 6k
8k 8k 8k
(16k FFT of a 1 kHz input signal)
10k 10k 10k Hz Hz Hz
12k 12k 12k
14k 14k 14k
16k 16k 16k
18k 18k 18k
20k 20k 20k
2k 2k 2k
4k 4k 4k
6k 6k 6k
8k 8k 8k
(16k FFT of a 1 kHz input signal)
10k 10k 10k Hz Hz Hz
12k 12k 12k
14k 14k 14k
16k 16k 16k
18k 18k 18k
20k 20k 20k
Figure 31. 0 dBFS FFT (HRM)
A ud io P re c is io n
+0 +0 +0 -10 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 -50 -50 -50 -60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
Figure 32. -60 dBFS FFT (HRM)
D -A C C IF IMD vs A MP L ITUD E 0 8 /0 5 /9 9 1 1 :1 1 :3 6
+0 +0 +0 -10 -10 -10 -20 -20 -20 -30 -30 -30 -40 -40 -40 -50 -50 -50
dBr A A dBr
d B r A
dBr A dBr A
d B r A
-60 -60 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90
-100 -100 -100 -110 -110 -110 -120 -120 -120 -130 -130 -130 -140 -140 -140
-100 -100 -100 -110 -110 -110 -120 -120 -120 -130 -130 -130
2k 2k
2k
4k 4k 4k
6k 6k 6k
8k 8k 8k
10k 10k 10k Hz
12k 12k 12k
14k 14k 14k
16k 16k 16k
18k 18k 18k
20k 20k 20k
-140 -140 -140
Hz Hz
2k 2k 2k
4k 4k 4k
6k 6k 6k
8k 8k 8k
10k 10k 10k Hz HzHz
12k 12k 12k
14k 14k 14k
16k 16k 16k
18k 18k
18k
20k 20k
20k
(16k FFT with no input signal)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 33. Idle Channel Noise FFT (HRM)
Figure 34. Twin Tone IMD FFT (HRM)
-60 -60
+0 +0 +0 -10 -10 -10
-70 -70
-20 -20 -20 -30 -30 -30
dBr AA dBr
dBr A
d B r A
-80 -80
d B r A
-40 -40 -40 -50 -50 -50 -60 -60 -60 -70 -70 -70 -80 -80 -80
-90 -90
-100 -100
-90 -90 -90
-100 -100 -100
-110 -110-60 -60 -50 -50 -40 -40 -30 -30 dBFS dBFS -20 -20 -10 -10 +0 +0
-110 -110 -110
20 20
20
50 50
100 100 100
200 200 200
500 500 Hz Hz Hz
1k 1k
2k 2k
5k 5k
10k 10k 10k
20k 20k
20k
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 35. THD+N vs. Amplitude (HRM)
Figure 36. THD+N vs. Frequency (HRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain System Two Cascade.
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5. PIN DESCRIPTIONS
SERIAL DATA INPUT DE-EMPHASIS / SCLK LEFT / RIGHT CLOCK MASTER CLOCK
No. 1 Pin Name SDATA
SDATA DEM/SCLK LRCK MCLK
1 2 3 4
8 7 6 5
AOUTL VA AGND AOUTR
ANALOG LEFT CHANNEL OUTPUT ANALOG POWER ANALOG GROUND ANALOG RIGHT CHANNEL OUTPUT
2 3 4 5 6 7 8
DEM/SCLK LRCK MCLK AOUTR AGND VA AOUTL
I/O Pin Function and Description I Serial Audio Data Input - two's complement MSB-first serial data is input on this pin. The data is clocked into the CS4334/5/6/7/8/9 via internal or external SCLK, and the channel is determined by LRCK. I De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or external serial clock input. I Left/Right Clock - determines which channel is currently being input on the Audio Serial Data Input pin, SDATA. I Master Clock - frequency must be 256x, 384x, or 512x the input sample rate in BRM and either 128x or 192x the input sample rate in HRM. O Analog Right Channel Output - typically 3.5 Vp-p for a full-scale input signal. I Analog Ground - analog ground reference is 0V. I Analog Power - analog power supply is nominally +5V. O Analog Left Channel Output - typically 3.5 Vp-p for a full-scale input signal.
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6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift - The change in gain value with temperature. Units in ppm/C.
7. REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4334/5/6/7/8/9 Evaluation Board Datasheet
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8. ORDERING INFORMATION:
Model CS4334-KS CS4335-KS CS4336-KS CS4337-KS CS4338-KS CS4339-KS CS4334-BS CS4335-BS CS4336-BS CS4337-BS CS4338-BS CS4339-BS Temperature -10 to +70 C -10 to +70 C -10 to +70 C -10 to +70 C -10 to +70 C -10 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C Package 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC Serial Interface 16 to 24-bit, I2S 16 to 24-bit, left justified 24-bit, right justified 20-bit, right justified 16-bit, right justified 18-bit, right justified, 32 Fs Internal SCLK mode 16 to 24-bit, I2S 16 to 24-bit, left justified 24-bit, right justified 20-bit, right justified 16-bit, right justified 18-bit, right justified, 32 Fs Internal SCLK mode
9. FUNCTIONAL COMPATIBILITY
CS4330-KS CS4339-KS CS4331-KS CS4334-KS CS4333-KS CS4338-KS CS4330-BS CS4339-BS CS4331-BS CS4334-BS CS4333-BS CS4338-BS
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10. PACKAGE DIMENSIONS
8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1 b c
D SEATING PLANE e A1
A L
INCHES DIM A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.189 0.150 0.040 0.228 0.016 0 MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.060 0.244 0.050 8
MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0 8
JEDEC # : MS-012
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DS248PP3
* Notes *

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